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Systémoví analytici

Povolanie: Systémoví analytici , dizajnér inteligentných systémov IKT/dizajnérka inteligentných systémov IKT
Bratislava-Staré Mesto, Karadžičova 14

82108

3700.00 €

11. 3. 2024

Dátum začiatku

What you'll be doing

 

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  • Working on high performance L2 Cache unit serving the needs of state-of-the art AI processing elements

    Skills required

     
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  • Requires 1 to 3 years of experience (will consider bright individuals even with lower experience) and the following skills:
     
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  • Understanding of high speed and low power processor pipeline designs / ASICs / SoCs and multi-core designs
     
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  • Strong understanding of computer architecture
     
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  • Experience with cache controller designs, understanding of cache coherency protocols, cache hierarchy
     
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  • Logic design experience with state of the art deep submicron technologies specifically low power design techniques
     
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  • Verilog / system Verilog / Synthesis / STA (Static timing analysis) / CDC / LINT
     
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  • Knowledge of ARM and x86 and multicore processor designs is a plus
     
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  • Knowledge of programming languages C, scripting (Perl / shell / python / awk) is a plus

  • 3700.00 €